Consumers continue to desire computer systems with higher performance and lower cost. To address higher performance requirements, computer chip designers have developed data processors having multiple processor cores along with a cache memory hierarchy on a single microprocessor chip. The caches in the cache hierarchy increase overall performance by reducing the average time required to access frequently used instructions and data. First level caches (L1) in the cache hierarchy are generally placed operationally close to a corresponding processor core. Typically, a processor core accesses its own dedicated L1 cache, while a last level cache (LLC) may be shared between more than one processor core and operates as the last cache between the processor cores and off-chip memory. The off-chip memory generally includes commercially available dynamic random access memory (DRAM) chips such as double data rate (DDR) synchronous DRAMs (SDRAMs).
The cache controllers store new entries in their corresponding cache arrays in response to accesses by the processor cores. If a processor core has modified data stored in a cache line, the cache controller determines when to write the “dirty” cache line back to the off-chip memory according to its writeback policy. For example, the cache controller may follow a writeback on eviction policy. However, delaying write back operations until the cache line is ready for eviction could degrade the overall performance of the microprocessor by causing the memory controller to inefficiently perform the writebacks and possibly stalling the processor core.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.